Probleme with LK204-25 I2C and cypress

LK/ELK/VK/PK/OK/MX/GLK/EGLK/GVK/GLT Series

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sberthelot
LCD?
Posts: 1
Joined: Tue Jul 25, 2006 9:49 am

Probleme with LK204-25 I2C and cypress

Post by sberthelot »

Hi, before sorry for my poor english :(

I try to make i2c communication between "cypress (cy8c29466) on psoceval1 cy3210" and LK204-25.

this is my code :

[i]include "m8c.inc" // include m8c specific declarations
include "psocapi.inc" // include User Module API specific declarations

export _main:

_main:

call I2CHW_1_Start
Call I2CHW_1_EnableInt
M8C_EnableGInt
Call I2CHW_1_EnableMstr
mov A,$50 ; Load slave address (7-bits)
mov X,I2CHW_1_WRITE ; Prepare for a write sequence (8th bit)
call I2CHW_1_fSendStart ; start condition, load previous slave adr and ack[/i]

i have put the pull up resistance (2kOhms)
no jumper on the LK for 50h adr
i put a scope on sda and scl signal:
i can see the start condition, the 7 bits adr, the 8TH R/W bit, but the 9th bit (ack) was at NACK status :(

could you explain to me why the LK dont ACK?

i have try RS232 befor I2C and all was fine.... no problem.

thx for your respond.[/img]



Edit: i have found my mistake........
50h its the 7 bit adr and 8th bit in the same byte
in my code, the adr of the LK become 2Eh in this case :lol:
Raquel
Matrix Orbital
Matrix Orbital
Posts: 834
Joined: Thu Aug 19, 2004 3:37 pm
Location: MO Office

Post by Raquel »

Hi sberthelot,

Thank you for posting on the forum.

Yes, it is a common mistake that 50h default address of Matrix Orbital modules is taken as 7 bit address, when in fact, this is already the full 8 bit address.

When addressing the module, (default) 50h is the write address and (default) 51h is the read address (the last bit is 0/1 corresponding the write/read bit).
Raquel Malinis
Design and Development
Matrix Orbital
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